1. Field of the Invention
The invention relates to the field of electrically erasable, programmable read-only-memory ("EEPROM") devices and, particularly, to an efficient contactless array configuration for the implementation of memory cells that rely on source-side injection for fast programming. Even more particularly, the invention relates to a contactless array configuration with shared program gates for erasable and programmable semiconductor memories based on enhanced hot-electron injection cells.
2. Field of the Prior Art
Recently, Flash EEPROM memories have gained substantial interest as the best solution for electrically-rewritable high-density nonvolatile data storage. These semiconductor memories combine the high integration density and high programming speed of EPROMs with the higher functionality of EEPROMs by offering electrical in-circuit erasability. Typically, Flash memories are distinguished from "classical" EEPROMs by their block (or sector) erase scheme. That is, in a Flash memory the byte-selective erasability of EEPROMs is sacrificed for the sake of a higher integration density. The possibility exist, however, to divide the memory in different sectors which can be erased separately.
At first, Flash memory was introduced for replacing EPROMs and battery-backed Random Access Memories ("RAMs") in measuring equipment (calibration, trimming, data storage), tuners and TV sets (programmable channel selection), and in microcomputers (microcode updates). On the other hand, new applications have arisen, such as solid-state disks for small computers and Personal Digital Assistants ("PDAs"), program storage for Digital Signal Processing ("DSP") chips and for portable equipment, smart cards, automotive applications (such as fuel injection control and Automatic Braking Systems ("ABS systems")) and neural networks. Additionally, a trend has arisen to integrate logic and nonvolatile memory on the same chip: the so-called embedded memories which require a compromise between performance, density and processing complexity.
Generally, as described below, three main classes of Flash memories can be identified.
The first class uses conventional channel hot-electron injection at the drain junction as a fast but power-consuming programming mechanism. Erasure is achieved by Fowler-Nordheim injection from the floating gate towards the source junction. See FIG. 1. The main advantage of this cell is the small area, which makes it well-suited for high density applications (so-called bulk memory). The main disadvantages are the high processing complexity and the high power consumption (in order to compensate for the intrinsically low programming efficiency), and the presence of major reliability problems (overerase, soft-write and short-channel effects, drain disturb), which compromise the scalability of this memory concept. On the other hand, the conventional NOR array configuration (see FIG. 2)--which is commonly used for this type of memory--requires 1/2 contact per bit. This is a yield limiting factor at the considered ever-increasing densities (currently 16 Megabit). A contactless version of such an array has also been proposed, however, at the expense of a complicated bitline segmentation scheme and a lower programming and read-out speed.
The second class uses bi-directional Fowler-Nordheim tunneling and is essentially derived from conventional FLOTOX EEPROMs (see FIG. 3). The main advantage is the very low power consumption which is required for Fowler-Nordheim programming. Therefore, the programming voltages can be generated on-chip, and operation from a single supply voltage is obtained. The main disadvantages are the very high voltages (20V) to be switched on-chip and the corresponding reliability issues (oxide defects, junction breakdown), the large transistor area, and the low programming speed. A smaller area can, however, be achieved by increasing the processing complexity and by reducing the gate coupling coefficient at the expense of even higher programming voltages. A typical high-density configuration for these memories is the NAND configuration (see FIG. 4), which suffers from a very high access time in the order of microseconds.
Faster programming can be achieved by using page-mode programming techniques, which, however, complicate circuit design. Finally, the scalability of this concept is highly questionable, especially because of the limitations with respect to tunnel oxide scaling.
The third class of Flash memory transistors emerged only a few years ago and was meant to combine the advantages of the previous two classes. Although entirely different transistor structures have been proposed, they all aimed at increased programming efficiency. The High Injection Metal-Oxide-Semiconductor (or HIMOS) transistor, which is described in co-pending applications having Ser. Nos. 08/275,016 and 08/080,225, belongs to this last category and, more specifically, it combines a low development entry cost with the remarkable features of the enhanced injection mechanism, yielding a low-cost, single-supply voltage, fast-programmable Flash memory technology, which requires only moderate voltages on-chip, and which shows a high immunity with respect to soft-write, overerase, short-channel and drain disturb effects. See FIG. 5. The triple-gate structure and the specific operation modes of this cell allow the implementation into a dense contactless array which partially compensates for the somewhat larger transistor area. This renders the HIMOS transistor into an attractive candidate for medium-density, cost-effective Flash EEPROM applications.
Once a transistor concept has been defined in a given process technology, it has to be designed in such a way that a practical memory organization is obtained. Moreover, the transistor properties have to be exploited in order to optimize the density of the resulting memory array, taking into account the main circuit-related parameters, such as disturb conditions, read-out current, and capacitive and resistive loads for the periphery circuits. Therefore, the basic layout of the transistor depends strongly on how different transistors are to be interconnected in a circuit. This is where the term "memory cell" comes in: the memory cell, as opposed to transistor, is the practical layout of the transistor which is repeatedly copied through mirroring or translation along its symmetry axes in order to produce the full memory array.
The advantages of optimizing memory cells for contactless arrays in EPROM and EEPROM memories have long been recognized. Esquivel et al., "High Density Contactless, Self Aligned EPROM Cell Array Technology", IEDM 1986, describe the principle in a conventional EPROM array, while Gill et al., "A 5 Volt Contactless Array 256K Bit Flash EEPROM Technology", IEDM 1988, describe a similar contactless array for Flash memories.
It is also well known that asymmetrical Flash memory transistors, which often use source-side injection as a programming mechanism, are well-suited for the implementation in contactless arrays. U.S. Pat. No. 5,212,541, issued May 18, 1993 to Bergemont, discloses such a contactless array for cells programmed through source-side injection. However, the coupling line which is mentioned in Bergemont's patent is provided for every separate row in the array, which causes a considerable overhead with respect to the density of the array. Furthermore, when referring to FIG. 6 in the Bergemont patent, it is noted that all cells are oriented in the same direction, which implies a virtual ground array configuration. Therefore, the Bergemont configuration is incorrect, since the source line cannot be shared between adjacent cells in a row without alternating the position of the source and drain junctions of the memory cells along each row.
U.S. Pat. No. 5,280,446, issued Jan. 18, 1994 to Ma et al., and U.S. Pat. No. 5,284,784, issued Feb. 8, 1994 to Manley, both disclose other examples of a contactless array for source-side injection cells. These configurations, however, also provide a separate control line for every column or row, respectively. The area overhead caused by these configurations can be largely relaxed by the use of an additional polysilicon layer, however, at the expense of using a complicated triple polysilicon technology.
The present invention substantially circumvents these drawbacks by introducing a shared program line scheme, which substantially reduces the area overhead caused by the program gates of the memory cells without adding additional processing steps. The concept of using a contactless array for the HIMOS cell described in co-pending applications Ser. Nos. 08/275,016 and 08/080,225 is mentioned in these applications at page 15, lines 26-35. In the present application, however, this concept is further refined and optimized to produce a practical array organization.